One primary motivation of circuit designers of silicon integrated circuits is to reduce the size of the chip space required for circuit components. Reducing the utilized chip space reduces the amount of power required to operate the chip, reduces the temperature of the circuit, and allows the circuit to operate faster. Some solutions have been proposed to create silicon integrated circuits on the nanometer scale (1×10−9 meters), or nanoscale, but each has limitations.
Much research is being dedicated to study nanoscale objects, and attempts have been made to build nanoscale objects in a controlled manner. Proposed solutions include the use of anodized aluminum templates, oriented block copolymers, self-assembled diblock copolymers, and patterning with packed layers of nanoscale objects. These approaches have significant limitations.
Nanoscale objects have been created with anodized aluminum templates. In this process, an aluminum layer is anodized to create openings through the layer. The openings in the anodized aluminum are used in an attempt to establish a grid of holes. These holes protrude down through the aluminum template to a substrate below. However, since the anodizing of the aluminum creates unpredictable patterns of openings in the aluminum layer, there is little control with respect to where the openings and the corresponding holes are located. There is little control over the size, shape, or arrangement of the openings.
Another approach to creating nanoscale objects utilizes diblock copolymers. With diblock copolymers, the order of a pattern of openings is controlled by nature. This approach does not provide regular patterns or spatially symmetric opening arrangements. There is no correlation with respect to distances and orientations, making placement of nanoscale objects random and difficult to incorporate into engineered structures that require a higher degree of order. Similar problems exist when using self-assembled copolymers. Templates fabricated using diblock copolymer or self-assembled copolymer approaches do not provide regular patterns or spatially symmetric opening arrangements.
Another approach is the microsphere method, where a substrate's surface is populated with nanoscale objects. When packing is achieved, the objects abut against each other, forming spaces where the objects abut to provide inclusions. The shape and size of the openings are determined by the spaces that are formed at the interstices where the objects contact. Thus, the range of opening geometries that can be generated is limited, and there is no control over the pattern's orientation.
None of the available methods provides the ability to create nanoscale structures on a substrate where the number, size, shape, pattern, orientation, and position of the structures can be controlled. Therefore, there exists a need for a method and system that can create nanoscale structures on a substrate where the number, size, shape, pattern, orientation, and position of the nanoscale structures can be controlled. If this could be done, structures, devices, and circuits could be manufactured on the nanoscale, and chip space could be reduced. As discussed below, embodiments of the invention accomplishes this in a unique and elegant manner.